1. Field of the Invention
In general, this invention relates to a method for producing multi-level, co-planar, metal/insulator interconnection layers for high performance semiconductor chips and more particularly to a method for making contact studs for interconnecting the metallization layers at different levels in said semiconductor chips.
2. Description of Related Art
A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of metal wires. In VLSI chips these metal patterns are multi-layered and separated by layers of an insulating material. Interconnections between the layers of metal wiring patterns are made by holes (or via-holes), which are etched through the insulator. Typical chip designs consist of one, two or three wiring levels.
The forming of an interconnection metallurgy system for integrated circuit devices has conventionally been done by blanket depositing a metal layer, forming a photoresist layer on the metal layer, exposing the resist to the desired metallurgy pattern, developing the resist, and subsequently etching the exposed portions of the underlying metal layer to thereby form the interconnection wiring. The wiring pattern was subsequently covered by an insulating layer, planarized and then another metallurgy pattern was then formed on said insulating layer. Contact between layers was made through via holes, until the desired interconnection wiring diagram was complete.
Interconnection of the multi-level wiring structure to the device contacts on the substrate was typically made by the incorporation of an access wiring layer.
In an effort to further reduce device processing time and reduce size, access wiring layers were replaced by via studs or vertical wires, known in the art as studs. Studs were now able to be placed directly on top of the device contacts to make interconnection with the above multi-level wiring system.
Studs are known to be formed by using what is termed an "expendable mask method" or "lift-off method", which was initially described and claimed in U.S. Pat. No. 2,559,389. Improvements to the basic lift-off method have been made, as for example in commonly assigned U.S. Pat. Nos. 3,849,136 filed Aug. 31, 1973 and 3,873,361 filed Nov. 29, 1973. However, the lift-off technique for forming stud metallurgy does not totally overcome the problems of: uniform deposition of stud metallurgy, planarity problems associated with achieving uniform stud height, high aspect ratio stud depositions, and electromigration tendencies of the preferred stud metallurgies.
An example of the problems associated with stud formation can be seen from the use of lift-off with aluminum as the stud metal. The aluminum must be deposited by evaporation; however, evaporation of aluminum is known to create problems of voids and irregularities in its formation.
Another problem associated with stud formation is the structural irregularities which are known to be created by the nature of the master-slice processing. For example, as master-slice processing causes variation in depth of contacts, the height of the deposited studs becomes variable such that the aluminum studs must be ion etched back to form a planar surface. (See, for example, U.S. Pat. No. 4,541,169.).
While there have been many techniques proposed for achieving planarity of studs, these techniques have all been based on the use of Ion Etch back with lift-off, (For example, U.S. Pat. Nos. 4,410,622; 4,470,874, and 4,541,169) wherein the results have not achieved consistent planarity and the methods have been limited to larger line widths and studs.
Moreover, with aluminum as a stud metal, there are added problems in terms of contact alloying/penetration, electromigration, and silicon particle formation. Silicon will form particles and thin films in the contact holes which results in the aluminum being isolated from the substrate surface. Moreover, with the ever-continuing reduction of dimensions in the device multi-level interconnection system, limits as to insulation and electromigration tolerances in using aluminum are encountered.
Electromigration problems associated with aluminum deposited on silicon type substrates have been proposed to be cured by use of tungsten films as diffusion barriers (M. L. Green and R. A. Levy, Technical Proceedings, SEMICON/EAST 85, Semiconductor Equipment and Materials Institute Meeting, September, 1985, pp. 57-63). However, defects "wormholes" originating at the tungsten/silicon interface and problems with preferential erosion of N+ implanted silicon versus P+ implanted silicon from LPCVD tungsten deposition have taught against the solitary use of LPCVD tungsten as the contact stud filler metallurgy.
In a more recent publication (U. Fritsch, G. Higelin, G. Enders and W. Muller; Technical Proceedings, V-MIC Conference Meeting; June 13, 14, 1988, pp. 69-75), the authors propose one possible solution to the defects associated with deposition of CVD tungsten in CMOS devices. Therein, the authors propose first depositing a titanium/titanium nitride diffusion barrier by sputtering followed by a CVD tungsten layer. However, this structure does not create a seed layer which matches the atomic structure of the CVD refractory metal which is to follow. Therefore, there can be interface problems between the CVD refractory fill metal and the titanium nitride layer such as mechanical separation and/or electrical resistance.
It is therefore an object of the present invention to produce a method for producing a multi-level co-planar metal and insulation interconnection system for VLSI semiconductor devices.
It is a further object of the present invention to produce planar studs for contacting the substrate to the first level of interconnection wiring.
It is a still further object of the present invention to produce interconnect studs, incapable of being produced with liftoff tolerances (i.e., stud widths of less than 1.5 .mu.m).
It is another object of the present invention to produce substrate contact studs of a non-reactive metal for void free deposition with low electromigration characteristics.
It is still another object of the present invention to provide a substrate contact stud structure useable with different component contacts.